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74HC374 Octal 3-State Non-Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The 74HC374 is identical in pinout to the LS374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, the outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. The HC374 is identical in function to the HC574A which has the input pins on the opposite side of the package from the output. This device is similar in function to the HC534A which has inverting outputs.
Features http://onsemi.com MARKING DIAGRAM
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC 374 ALYW G G
* * * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 266 FETs or 66.5 Equivalent Gates This is a Pb-Free Device
HC374 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
March, 2007 - Rev. 0
1
Publication Order Number: 74HC374/D
74HC374
PIN ASSIGNMENT LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 3 4 7 8 13 14 17 18 11 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS OUTPUT ENABLE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK
FUNCTION TABLE
1 PIN 20 = VCC PIN 10 = GND Inputs Output Enable L L L H Clock D H L X X Output Q H L No Change Z
OUTPUT ENABLE
L,H, X
X = don't care Z = high impedance
ORDERING INFORMATION
Device 74HC374DTR2G Package TSSOP-20* Shipping 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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74HC374
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MAXIMUM RATINGS
Symbol VCC Vin Iin Iout ICC PD Tstg TL Vout Parameter Value Unit V V V mA mA mA mW _C _C DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 450 - 65 to + 150 260 DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (TSSOP Package) TSSOP Package
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 - 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns
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74HC374
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.48 2.98 5.48 0.10 0.10 0.10 0.26 0.26 0.26 0.1 0.5 v 85_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.34 3.84 5.34 0.10 0.10 0.10 0.33 0.33 0.33 1.0 5.0 v 125_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.90 4.40 5.90 2.20 3.70 5.20 0.10 0.10 0.10 0.40 0.40 0.40 1.0 10 Unit V
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V
V V
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V mA mA
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA
ICC
6.0
4.0
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC374
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 6 15 30 35 125 80 25 21 150 100 30 26 150 100 30 26 75 27 15 13 10 15 v 85_C 5 10 24 28 155 110 31 26 190 125 38 33 190 125 38 33 95 32 19 16 10 15 v 125_C 4 8 20 24 190 130 38 32 225 150 45 38 225 150 45 38 110 36 22 19 10 15 Unit MHz
tPLH tPHL
Maximum Propagation Delay, Input Clock to Q (Figures 1 and 5)
ns
tPLZ tPHZ
Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6)
ns
tPLZ tPHZ
Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6)
ns
tTLH tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 5)
ns
Cin Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State)
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 34 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC374
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TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit v 85_C Symbol tsu Parameter Figure 3 VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C Min 50 40 10 9 5.0 5.0 5.0 5.0 60 23 12 10 1000 800 500 400 Max v 125_C Min 65 50 13 11 5.0 50 5.0 5.0 75 27 15 13 1000 800 500 400 Max Min 75 60 15 13 5.0 5.0 5.0 5.0 90 32 18 15 1000 800 500 400 Max Unit ns Minimum Setup Time, Data to Clock th Minimum Hold Time, Clock to Data 3 ns tw Minimum Pulse Width, Clock 1 ns tr, tf Maximum Input Rise and Fall Times 1 ns
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10% tW 1/fmax tPLH Q 90% 50% 10% tTLH tTHL Q 50% tPHL Q 50% tPZH tPHZ 90% tf VCC 50% GND tPZL tPLZ 10% HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
VCC
OUTPUT ENABLE
GND
Figure 1.
Figure 2.
VALID VCC DATA 50% GND tsu th VCC CLOCK 50% GND
Figure 3.
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74HC374
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
D0 3 D C Clock 11 Q
D1 4 D C Q
D2 7 D C Q
D3 8 D C Q
D4 13 D C Q
D5 14 D C Q
D6 17 D C Q
D7 18 D C Q
Output 1 Enable
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
Figure 6. Expanded Logic Diagram
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74HC374
PACKAGE DIMENSIONS
TSSOP-20 CASE 948E-02 ISSUE C
20X
K REF
M
2X
L/2
20
11
J J1 B -U- N
L
PIN 1 IDENT 1 10
0.15 (0.006) T U
S
A -V-
N F DETAIL E -W-
DIM A B C D F G H J J1 K K1 L M
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC374
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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74HC373/D

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